One of the steps of designing an integrated circuit layout is to arrange for clock signals to be supplied to clocked cells of the circuit. A computer based design tool is used to automatically design a clock signal supply network (clock tree) according to predetermined design rules. The clock tree has multiple branches to deliver clock signals to different circuit cells, at different locations, on an integrated circuit die. The branches typically include active circuit cells through which the clock signal passes. Typical active cells include repeater cells for preserving the clock signal in long signal paths, and clock gate cells for selectively blocking or applying the clock signal. In a balanced clock tree, the branches are designed to have generally the same signal path length in each branch in an attempt to reduce clock skew between the branches.
Controlling clock skew is an important part of the design process. Clock skew affects the relative timing at which different cells in the integrated circuit operate. Clock skew can be a limiting factor on the maximum operating speed of one or more parts of the integrated circuit or the integrated circuit as a whole. In practice, undesirable clock skew between two or more branches of a clock tree remains a significant design problem. The problem is becoming increasingly apparent as greater demands are made on speed, performance, complexity and fabrication size and density of integrated circuits. Current automatic design tools for placing clock trees lack sufficient refinement for optimizing clock trees in demanding or speed critical designs.